9:00 AM

9:15 AM

Morning Welcome

Jack Gidding

CEO, Strategic Technology Analysis Center

9:15 AM

9:25 AM

STAC Update: STAC-AI

James Corcoran

Head of AI & Analytics, Strategic Technology Analysis Center

STAC Update

9:25 AM

9:30 AM

Future Ready AI

Michael Watson

Senior Director of Field Application Engineering, Supermicro

Innovation Roundup

9:30 AM

9:35 AM

Simplifying GenAI and RAG Data Pipeline Complexity

Robert Glanzman

Global Strategic Alliances Principal Architect, Pure Storage

Innovation Roundup

9:35 AM

9:40 AM

Kove:SDM™: Real Memory Software-Defined

John Overton

CEO, Kove

Innovation Roundup

9:45 AM

10:25 AM

Is breaking up hard to do? Storage and memory disaggregation for financial HPC

Dr. Christoph Lameter

Distinguished Software Engineer, Ampere Computing LLC

Attila Narin

Vice President of Cloud Engineering, Oracle

Robert Glanzman

Global Strategic Alliances Principal Architect, Pure Storage

John Overton

CEO, Kove

Panel

10:25 AM

10:55 AM

Break

Networking

10:55 AM

11:05 AM

STAC Update: Tick Analytics, Risk Computing & Strategy Backtesting

James Corcoran

Head of AI & Analytics, Strategic Technology Analysis Center

STAC Update

11:05 AM

11:20 AM

Every Bit Counts: Next Generation Arithmetic and Big Memory

Kurt Keville

Chief Architect, SemiconDx & Project Isango

Tech Brief

11:20 AM

11:25 AM

Lenovo in Finance

Marc Fisher

Director, HPC/AI Solution Sale, Lenovo

Innovation Roundup

11:25 AM

11:30 AM

Low Latency AI with the AMD Alveo V80 Accelerator

Michael McGuirk

Sr Product Manager, Data Center, AMD

Innovation Roundup

11:30 AM

11:35 AM

Latest Innovation at Oracle Cloud for Fast Compute and Fast Data

Attila Narin

Vice President of Cloud Engineering, Oracle

Innovation Roundup

11:35 AM

11:40 AM

Josh Kalina

Sr. Pre-Sales Engineer, KX

Innovation Roundup

11:45 AM

12:00 PM

Fast Compute: How fast is Fast?

Basile Henry

Senior Software Developer, Myrtle.ai

Tech Brief

12:00 PM

12:35 PM

The new table stakes? Advanced compute for time series modeling

David Don

VP Algorithmic Trading, Trading Technologies

Krishnan Iyengar

Group Vice President-Strategic Initiatives, Oracle

Josh Kalina

Sr. Pre-Sales Engineer, KX

Dr. Mark Bennett

Senior Data Scientist, NVIDIA

Panel

12:35 PM

1:35 PM

Lunch

Networking

1:35 PM

1:45 PM

Afternoon Welcome

Jack Gidding

CEO, Strategic Technology Analysis Center

1:45 PM

1:55 PM

STAC Update: Fast Data

Jack Gidding

CEO, Strategic Technology Analysis Center

STAC Update

1:55 PM

2:00 PM

Beeks Analytics: Distributed Packet Capture, Streaming Decodes and... Edge Intelligence

Matt Cretney

Head of Product Management, Beeks

Innovation Roundup

2:00 PM

2:05 PM

Why Hybrid Cloud for Market Data Distribution?

Steven Riley

OCI Cloud Architect, Oracle

Innovation Roundup

2:05 PM

2:10 PM

AI/HPC Solutions for Financial Services

Michael Watson

Senior Director of Field Application Engineering, Supermicro

Innovation Roundup

2:15 PM

2:30 PM

Stress relief: Using AI to analyze trading-platform telemetry

Raymond Russell

Managing Director of Product Management, Pico

Tech Brief

2:30 PM

3:00 PM

Break

Networking

3:00 PM

3:05 PM

STAC Update: Tick To Trade

Jack Gidding

CEO, Strategic Technology Analysis Center

STAC Update

3:05 PM

3:20 PM

No more flying blind: Detecting bad time in time to do something

Ciaran Kennedy

Sales, Safran

Tech Brief

3:20 PM

3:25 PM

A Full Featured Market Data Platform using FPGAs

Cliff Maddox

Director of Business Development, Novasparks

Innovation Roundup

3:25 PM

3:30 PM

Ultra Low Latency Trading with the latest Alveo Accelerators and AMD CPU's

Michael McGuirk

Sr Product Manager, Data Center, AMD

Innovation Roundup

3:35 PM

3:40 PM

Create your ULL FPGA application in 5 easy steps with nxFramework

Laurent de Barry

VP, Ultra Low Latency Trading, Exegy

Innovation Roundup

3:40 PM

3:45 PM

Deploy HFT Accelerators Faster with COFE!

Paul Graykowski

Product Marketing Director, Cadence

Innovation Roundup

3:45 PM

4:20 PM

Show me some love: Improving the FPGA “Engineer Experience”

Justin Thiel

Hardware Engineer, Hudson River Trading

Dr. David Lariviere

Clinical Professor of Financial Engineering, University of Illinois

Daniel Wisehart

FPGA & ASIC Engineer

Matthew Certosimo

Data Center FPGA Field Application Engineer, AMD

Paul Graykowski

Product Marketing Director, Cadence

Panel

4:20 PM

5:20 PM

Reception

Networking